Memory array write ports write data into the memory cells of synchronous memory arrays. They are used in various environments such as in memory controllers and microprocessors that have on-board memory arrays.
With reference to FIGS. 1 through 3 and particular reference to FIG. 1, a typical array write port 75 is shown for writing data into a conventional memory array 85. The memory array 85 includes an array of m rows by n columns of memory cells 87.
Array write port 75 generally includes row address decoders UR1 through URm and a write driver section, which includes write gates UC1 through UCn. Each row address decoder receives Row Address and Clock signals at its inputs and outputs a Row (e.g., Row 1, Row m) enable signal to each cell within its associated row. The Clock is a conventional two-phase clock. The Row Address signal consists of multiple address line bits for selecting (identifying) a unique address for each of the m rows within the system. Thus, the Row Address inputs for each row address decoder could actually include inputs (inverted or non-inverted) for each address line in order to identify a specific row. When the "correct" address is input from the Row Address line to a given row address decoder, an active (e.g., High) Row signal is output from the decoder if the clock is High. The active Row signal enables each cell within the row to be written to if its associated column is also activated.
The writegates UC1 through UCn each have inputs for receiving the clock signal, write data, and a column address signal (which is not shown). When activated, the write gate outputs a WData signal to each cell within its column for writing the WData value into one or more of these cells whose row is enabled by a Row enable signal. Each write gate has decoding capability for decoding an associated column address from the column address signal. If the column address for a given gate is present and the clock signal is active, the WData value applied at the gate's input will be outputted from the write gate and thus written to any cell in its column that has an active Row signal. With this array write port, data may be written to individual cells or even to whole rows of memory cells 87.
FIG. 2 shows the relevant portion of a typical memory cell 87. Memory cell 87 generally includes FETs Q1-Q4, which form a cross-coupled inverter pair, FETs Q5, Q6, which form a cell write port, and a cell read port (not shown). PFET Q1 and NFET Q2 are connected in a conventional inverting arrangement with their gates and drains tied together. Likewise, PFET Q3 and NFET Q4 are connected in the same way as an inverter. The Q3/Q4 gates are coupled with the Q1/Q2 drains to form a Data node for storing data in the cell, and the Q1/Q2 gates are coupled with the Q3/Q4 drains to form an NData (not Data) node for storing the data complement. The cell write port includes NFETs Q5 and Q6. The Q5 and Q6 drains are connected to the NData and Data nodes, respectively. Their gates are tied together and serve as the input for receiving the Row enable signal from the array write port 75. The source of Q5 is an NBit input with the source of Q6 being a Bit input. These Bit and NBit inputs function together as a differential input for receiving a WData signal in order for data to be written into the Data and NData nods. (Thus, when memory cells 87 are used with array write port 75, write drivers 315 provide differential WData signals.) When Row is active (or High), the value of WData is written into the Data/NData nodes through either Q5 or Q6 that is, if WData is High (i.e., Bit is sufficiently High relative to NBit), then Q5 turns on and pulls down NData (if not already Low), which ensures that Data will be High. Likewise, if WData is Low (i.e., NBit is High relative to Bit) and Row is High, then a High is written into NData and a Low is written into the Data node.
FIG. 3 shows a timing diagram for the various signals in the array write port 75 when WData is written into a memory cell. The diagram shows the clock signal 100, the Row signal 110, the WData signal 120, and the state of the cell data 130. When the clock is High and a Row signal goes High, WData is written into a memory cell. As shown at 130, after the Row goes High and the WData is asserted, old data at 132 is replaced with the new data 134 from the WData signal. One clock phase is used to actively write the data, and the other phase is used to recover and set up for the next clock cycle.
One drawback of such an array write port is that only one row of data maybe written into the memory array during each clock cycle. One solution to overcome this problem has been to utilize multiple array write ports connected in parallel across the cell write port of a memory array. In this way, each cell or row of cells can be independently written to with each array write port. This solution may not be practicable, however, in most IC applications where component and wire resources are at a premium.
Accordingly, what is needed is an improved scheme for writing data into a memory array.